snippet modelsim_min "simulate simple file" 
quit -sim
# compile file

vsim -t ps -voptargs=+acc=rn  work.top_tb

log -r /*
radix 16

do wave.do

run 10us
endsnippet

snippet modelsim_template "Description" b
quietly set prompt  "Please enter correct parameter. 
                TEST_IIC_CORE    -- simulate iic core
                TEST_MS8537		 -- simulate ms5837 driver
                "

if { $argc == 0} {
    puts $prompt
    return
} 

set TEST_SET [list TEST_IIC_CORE TEST_MS8537]
if { [lsearch -exact $TEST_SET \$1] < 0 } {
    puts "current input is \[ \$1 \]"
    puts $prompt
    return
}

quit -sim

if { [string equal $tcl_platform(os) "Linux"] == 1 } {
    source "$env(HOME)/vimrc/tcl/sim.tcl"
} else {
    source "$env(HOME)/tcl/sim.tcl"
}
::Sim::map_vivado2018_03_questasim_2021_2_1_lib

# compile file

# load ip

# vsim 



log -r /*
radix 16

do wave.do

run 10us
endsnippet

snippet modelsim_vsim_vivado  "run vsim command"
vsim -t ps -voptargs=+acc=rn +notimingchecks \
   -L secureip \
   -L simprims_ver \
   -L unifast \
   -L unifast_ver \
   -L unimacro \
   -L unimacro_ver \
   -L unisim \
   -L unisims_ver \
   glbl \
   work.tb
endsnippet

snippet modelsim_vsim_ise  "ise project simulate script"
vsim -t ps -voptargs=+acc=rn +notimingchecks \
   -L secureip \
   -L unisims_ver \
   -L unimacro_ver \
   -L xilinxcorelib_ver \
   glbl \
   work.tb
endsnippet


snippet modelsim_altera  "altera simulate script"
quit -sim
# 可以不手动建立library
#vlib    work
#vmap    work work

set env(ALTERA_LIB)         altera18.0_questasim_10.6c_lib
set env(LIB_PATH)           F:/crack/
vmap   \$env(ALTERA_LIB)     \$env(LIB_PATH)\$env(ALTERA_LIB)

#工程所需要的文件
vlog -sv -incr ../tb/top_tb.sv

vsim -t ps -voptargs=+acc=rn -L \$env(ALTERA_LIB) work.top_tb

log -r /*
radix 16

do wave.do

run 20us
endsnippet

snippet modelsim_vivado_pos "run Post-Implementation Timing Simulation"
vlog -sv -incr ../bench/${1:sim_tdc_top.sv}
file copy -force ${2:../vivado/main/main.sim/sim_1/impl/timing/questa/sim_tdc_test_time_impl.sdf} .
vlog -sv -incr ${3:../vivado/main/main.sim/sim_1/impl/timing/questa/sim_tdc_test_time_impl.v}

vsim -t ps -voptargs=+acc=rn +notimingchecks \
   -L secureip \
   -L simprims_ver \
   -L unifast \
   -L unifast_ver \
   -L unimacro \
   -L unimacro_ver \
   -L unisim \
   -L unisims_ver \
   glbl \
   work.${4:sim_tdc_test}


log -r /*
radix 16

do wave.do

run 10us

endsnippet
